wafer.space Community - Huh ... I'd like to know about those

12:57

It will mainly be about the logos: besides the QR code, we will also add a readable ID, which will look like this:

12:57

12:58

And for the bonding, it was suggested that the opposite corner should be empty to make it is easier to differentiate. The wafer.space logo will likely be moved in the top left corner. So only the bottom right corner can be used for a user logo.

Ok, we have a custom bonding setup anyway ( and the changes discussed in #cob would make TT incompatible anyway ) so that shouldn't be an issue.

tnt

Ok, we have a custom bonding setup anyway ( and the changes discussed in #cob would make TT incompatible anyway ) so that shouldn't be an issue.

Oh, custom bonding? Can I read enough on it two weeks from now to make at least an attempt at respecting the package inductance?

Huh no ...

13:14

The wire we use is the same, posted in some of the picture, the PCB we wirebond to is on the TT github ... feel free to run an EM simulation if you fancy it, but that's not something we will do as it's inconsequential to 99.99% of TT users ...

tnt

The wire we use is the same, posted in some of the picture, the PCB we wirebond to is on the TT github ... feel free to run an EM simulation if you fancy it, but that's not something we will do as it's inconsequential to 99.99% of TT users ...

That's enough documentation for me then.

Because of the COB process that means you have to use our big standard breakout so I'm not sure it'll be suitable for anything "high speed" in any case. Processes where you can get the QFN ( sky or ihp ) are more suitable. I'm hoping TT would also offer "bare chip" bonded to a small COB PCB like the W.S one of run.1. but not sure that will happen, that's not my decision.

tnt

Because of the COB process that means you have to use our big standard breakout so I'm not sure it'll be suitable for anything "high speed" in any case. Processes where you can get the QFN ( sky or ihp ) are more suitable. I'm hoping TT would also offer "bare chip" bonded to a small COB PCB like the W.S one of run.1. but not sure that will happen, that's not my decision.

Huh, are you not doing the same mezzanine plug (just different pinout/bonding diagram) as https://discord.com/channels/1361349522684510449/1361349523724570941/1501331867973193728 ?

15:10

(I couldn't find anything that clearly looked like a COB PCB on the TT GitHub that sounded like it applied; the "best" I could find was cobbler?) (edited)

I'd assume TT won't put all 1k dies of the ttgf0p3on the fancy breakout boards if there's sufficient interest in some going through the W.S COB "packaging" line, but even if not, I don't think extracting an analog pin pair to HF-appropriate and probing-suitable pads/pins would be too much for @azonenberg 's rework skills.

https://github.com/htfab/breakout-ttgf0p2-cob/tree/main

15:21

We wouldn't put 1k dies on it ... just what we deem necessary and just not do anything with the rest.

Hmmm, if it's JLC04161H-3313, they should be 50Ω single-ended/90~95Ω differential.

@stuart Do we know what the stackup of the PCBs we use for production is ?

I don't have to know until in those about 14 days from now.

after I have a functional design filed, and if I have several days left until the deadline, I would work to tune performance with PEX to the reasonably-accessible outside interface. I'd not need anything detailed I couldn't quick-maths from the bonding diagram and the analog mux structure before then.

tnt

@stuart Do we know what the stackup of the PCBs we use for production is ?

Which boards/production?

stuart

Which boards/production?

ttgf0p3 COB/"package"

18:04

I don't need to know any sooner than ~14 days from now.

namibj

I'd assume TT won't put all 1k dies of the ttgf0p3on the fancy breakout boards if there's sufficient interest in some going through the W.S COB "packaging" line, but even if not, I don't think extracting an analog pin pair to HF-appropriate and probing-suitable pads/pins would be too much for @azonenberg 's rework skills.

I have access to a gold ball bonder at work. Old K&S manual unit

18:24

if i can get them to OK me using it for a nonbillable project, I can probably rebond a bare die if i had 1-2 old dies on the same process to dial in the settings on

18:24

(like not remove existing bonds, but doing my own COB from a never-bonded die that breaks out to SMA or something)

Give me 15 minutes to get home.

namibj

ttgf0p3 COB/"package"

We haven't made any PCBs for these, only 0p2 and 0p1

@stuart Well I'm assuming we use the same 4l stackup every time ?

stuart

We haven't made any PCBs for these, only 0p2 and 0p1

I'm hoping those choices happen with a few days to spare until the GDS deadline for me filing the last tile revision, though. As said though, no rush from me just trying to get a bit of information going and then go offline for the weekend (3 very long days)

azonenberg

I have access to a gold ball bonder at work. Old K&S manual unit

@Andrew Wingate - FYI

Tim 'mithro' Ansell

@Andrew Wingate - FYI

Cool! Also sorry, I think I'm missing some context. Are you in the Chicago area @azonenberg?

No, Seattle

For TTGF0p1 and TTGF0p2 we used JLCPCB's standard 1.6mm FR-4 4 layer PCBs with ENIG

20:34

For the Wafer Space panels we used JLCPCB's 4-layer 0.8mm thick PCB with ENIG, though we are also trying some 2-layer panels at the moment

stuart

For TTGF0p1 and TTGF0p2 we used JLCPCB's standard 1.6mm FR-4 4 layer PCBs with ENIG

If it doesn't change the shown cost, I'd suggest clicking the "specify stackup" and just keeping the suggested one, that way it's at least known. I think in some cases there may be more than one choice in the "cheap" tier to pick from, though. But it confirms my assumptions that it's likely that JLC04161H-3313. (It's probably the stackup you got without specifying on the 1.6mm 4L's.)

1

@stuart But production boards shipped to users will be made by Sam right ? What stackup do they use ?

tnt

@stuart But production boards shipped to users will be made by Sam right ? What stackup do they use ?

This very much depends on the qtys we're making and what the priority is. For WS the priority (for now and afaiu at least) has been lowest cost.